Intel Xeon processors (Sapphire Rapids) support HBM

Intel Xeon processors (Sapphire Rapids) support HBM

Intel has prepared a programming guide that contains information about innovations in future processors for developers to use. In particular, the document found confirmation that the next generation Intel Xeon processors, codenamed Sapphire Rapids, support High Bandwidth Memory (HBM). The manual mentions 0220H – HBM command / address parity error and 0221H – HBM data parity error. They are intended to address bugs when working with HBM.

Working with HBM is one of the many innovations at Sapphire Rapids. Others include an eight-channel DDR5 memory controller supplemented with a Data Streaming Accelerator (DSA). To connect to all external accelerators, the platform uses the PCIe 5.0 protocol paired with the CXL 1.1 standard to ensure cache consistency.

The source recalls that Sapphire Rapids is not the first server processor to support HBM. The Top500 supercomputer Fugaku is based on 48-core Fujitsu A64FX processors with HBM memory.

Intel Xeon processors (Sapphire Rapids) support HBM

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